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HD151012
8-bit Binary Programmable Counter with Synchronous Preset Enable
ADE-205-132 (Z) Preliminary 1st. Edition Mar. 1996 Description
The HD151012 has 8-bit binary down counter and D-type Flip Flop. The counter can set up to max 256 counts and synchronous preset (SPE) input can preset the data. When the count value is 0, the next clock pulse presets the data to invert the output. D-type Flip Flop takes the counter output as clock pulse, whose data is transferred to output at the rise edge. It is applied to generate AC signal for STN type liquid crystal and general-use divider.
Features
* High speed operation tpd (CLK or CLK to Q) = 35 ns (typ) * High output current Fanout of 10 LS TTL Loads * Wide operating voltage VCC = 2 to 6 V * Low supply current (Ta = 25C) ICC (Static) = 4 A (max)
HD151012
Function Table
Control Inputs CLR H X L H PR H X H L SPE H L -- -- Mode Generally count Synchronous preset Initialize of Q output Initialize of Q output Operation Description Down count at the rise edge of clock (CLK) Down count at the fall edge of clock (CLK) Jn data is preset at the rise of clock (CLK), the fall of clock (CLK) Initialize of Q = "L" Initialize of Q = "H"
Notes: 1. Synchronous preset (SPE) input can set max 256 down counts. 2. When the count value is 0, the next clock pulse presets the data to invert the output. 3. CLR and PR inputs initialize output state. H : High level L : Low level X : Immaterial -- : Irrespective of condition
Pin Arrangement
J0 1 J1 2 J2 3 J3 4 J4 5 J5 6 J6 7 GND 8
16 VCC 15 CLK 14 CLK 13 Q 12 PR 11 SPE 10 CLR 9 J7
(Top view)
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HD151012
Pin Description
Pin Name Input pins J0 to J7 CLK, CLK SPE PR CLR Output pins Q Pin Description Count data input for option Clock inputs Preset input for Jn data Preset input for D-type Flip Flop (Initialize "L" at Q output) Clear input for D-type Flip Flop (Initialize "H" at Q output) Output for D-type Flip Flop CLK : Rise edge trigger CLK : Fall edge trigger
Absolute Maximum Ratings
Item Supply voltage Input / output voltage VCC, GND current Output current / pin Power dissipation Storage temperature Input diode current Output diode current Symbol VCC VIN/V OUT I CC, IGND I OUT PT Tstg I IK I OK Ratings -0.5 to 7.0 -0.5 to VCC +0.5 50 25 500 -65 to 150 20 20 Unit V V mA mA mW C mA mA
Notes: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 2. All voltage values except for differential input voltage are with respect to network ground terminal.
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HD151012
Recommended Operating Conditions
Item Supply voltage Input/output voltage Operating temperature Input rise/fall time*
1
Symbol VCC VIN/ OUT Topr VCC = 2.5 V VCC = 4.5 V VCC = 5.5 V t r, t f
Min 2 0 -40 0 0 0
Typ -- -- -- -- -- --
Max 6 VCC +85 1000 500 400
Unit V V C ns
Note:
1. This item guarantees maximum limit when one input switches.
Logic Diagram
J0 J1 J2 J3 J4 J5 J6 J7
J0 8-bit binary counter J1 J2 J3 J4 J5 J6 J7
CLK CLK CLK
PR PR D CO SPE CK CLR SPE CLR Q Q Q
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HD151012
Electrical Characteristics
Ta = 25C Item High level input voltage Symbol VIH VCC 2.0 4.5 6.0 2.0 4.5 6.0 Low level input voltage VIL 2.0 4.5 6.0 2.0 4.5 6.0 High level output voltage VOH 2.0 4.5 6.0 4.5 6.0 Low level output voltage VOL 2.0 4.5 6.0 4.5 6.0 Input capacitance Supply current I IN I CC 6.0 6.0 Min 1.5 3.15 4.2 1.5 3.15 4.2 -- -- -- -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- 2.0 4.5 6.0 4.31 5.80 0.0 0.0 0.0 0.17 0.18 -- -- Max -- -- -- -- -- -- 0.5 1.35 1.8 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.1 4.0 Ta = -40 to 85C Min 1.5 3.15 4.2 1.5 3.15 4.2 -- -- -- -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- Max -- -- -- -- -- -- 0.5 1.35 1.8 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 1.0 40.0 mA mA I OL = 4 mA I OL = 5.2 mA VIN = VCC or GND VIN = VCC or GND V VIN = VIH or VIL I OH = -4 mA I OH = -5.2 mA I OL = 20 mA V VIN = VIH or VIL I OH = -20 mA V J0 to J7 SPE PR, CLR CLK, CLK Unit V Test Conditions J0 to J7 SPE PR, CLR CLK, CLK
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HD151012
Switching Characteristics (CL = 50 pF, tr = tf = 6 ns)
SymItem Maximum clock frequency bol f max VCC 2.0 4.5 6.0 Output rise/fall time t TLH t THL 2.0 4.5 6.0 Propagation delay time t PLH t PHL 2.0 4.5 6.0 t PLH t PHL 2.0 4.5 6.0 Pulse width (CLK, CLK, PR, CLR) tw 2.0 4.5 6.0 Setup time (Jn - CLK, CLK) (SPE, CLK, CLK) Hold time (Jn - CLK, CLK) (SPE, CLK, CLK) Input capacitance Power dissipation capacitance* 1 Note: CIN CPD th ts 2.0 4.5 6.0 2.0 4.5 6.0 -- -- Ta = 25C Min -- -- -- -- -- -- -- -- -- -- -- -- 80 16 14 100 20 17 15 10 5 -- -- Typ -- 36 -- 30 8 7 -- 35 -- -- 18 -- -- -- -- -- -- -- -- -- -- 5 48 Max 4 20 24 75 15 13 300 60 53 150 30 25 -- -- -- -- -- -- -- -- -- 10 -- Ta = -40 to 85C Min -- -- -- -- -- -- -- -- -- -- -- -- 100 20 17 125 25 21 15 10 5 -- -- Max 3 16 19 95 19 16 380 75 65 185 38 32 -- -- -- -- -- -- -- -- -- 10 -- pF pF ns ns ns PR or CLR to Q CLK or CLK to Q ns Unit MHz Test Conditions
1. CPD is equivalent capacitance inside of the IC calculated from the operating current without load (see test circuit). The average operating current without load is calculated according to the expression below. I CC (opr) = CPD * VCC * fIN + ICC
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HD151012
Test Circuit
VCC Input Pulse generator See Function Table Zout = 50 Input Pulse generator Zout = 50 VCC
J0 J1 Output Q
J7 CLK CLK SPE PR CLR CL
Note:
1.
CL includes probe and jig capacitance.
Waveforms - 1
tw 6 ns tw 6 ns 90 % 90 % 50 % 50 % 10 % t PLH 90 % t PHL 90 % 50 % 10 % t THL
CLK
VCC
CLK
10 %
GND
VOH
Q
10 %
50 % t TLH
VOL
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HD151012
Waveforms - 2
6 ns 90 % 90 % 50 % 10 % 10 % ts
VCC
Jn
GND
90 % 50 %
CLK
VCC
CLK
10 %
10 % 6 ns
GND VOH
F/F Output
*1
50 %
Internal delay
VOL
Waveforms - 3
6 ns 90 % 90 % 50 % 10 % th 10 %
VCC
Jn
GND VCC
CLK
50 %
90 %
CLK
10 %
10 % 6 ns
GND VOH
F/F Output
*1
50 %
Internal delay
VOL
Note:
1.
F/F output is internal signal of IC.
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HD151012
Waveforms - 4
6 ns 90 % 90 % 50 % 10 % 10 % ts
VCC
SPE
GND
90 % 50 %
CLK
VCC
CLK
10 %
10 % 6 ns
GND VOH
F/F Output
*1
50 %
Internal delay
VOL
Waveforms - 5
6 ns 90 % 90 % 50 % 10 % th 10 %
VCC
SPE
GND VCC
CLK
50 %
90 %
CLK
10 %
10 % 6 ns
GND VOH
F/F Output
*1
50 %
Internal delay
VOL
Note:
1.
F/F output is internal signal of IC.
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HD151012
Waveforms - 6
tf 90 % tr 90 % 50 % 10 % tw tf 90 % tr 90 % 50 % 10 % tw t PHL t PLH
VCC
CLR
50 % 10 %
GND
VCC
PR
50 % 10 %
GND
VOH Q
50 % 50 %
VOL
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HD151012
Timing Chart
CLK
SPE
J0
J1
J2
J3
J4

J5 J6 J7 (CO=SPE) CLR (Initialize of CLR) Q PR (Initialize of PR) Q Count 5 4 3 2 1 0 3 2 1 0 35 34 11
HD151012
Example of Application Circuit
AC Signal Generator for STN Type Liquid Crystal Panel
Initialize counter: 50
J0 J1 J2 J3 J4 J5 J6 GND
V CC CLK CLK Q PR SPE CLR J7 * *
Note:
When initializing output D-F/F apply "L"
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HD151012
Timing Chart
Example of AC Signal Generator
1 2 3 49 50 51 52 53 101 102 103 104
CLK
SPE J0
J1
J2
J3 50 J4

J5 J6 J7 (CO=SPE) CLR Q PR Q Count 50 49 48 2 1 0 50 49 1 0 50 49
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HD151012
Package Dimensions
Unit : mm
TTP-16DA 5.20 5.4 Max 4.50 Max 16 9 4.40 1 0.20 0.10 8 0.65 0.10 M 6.40 0.20
0.10
0.17 0.05
1.10 Max
0.03 Min 0.1Max
0 - 10
0.50 0.10
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HD151012
Package Dimensions
Unit: mm
5.00 5.30 Max 16 9 4.40 1
0.08 *0.22 + 0.07 -
8 0.65 1.0 6.40 0.20 0 - 8 0.50 0.10
0.20 0.06
0.13 M 0.65 Max
*0.17 0.05 0.15 0.04
1.10 Max
0.10
0.07 +0.03 -0.04
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Mass (reference value)
TTP-16DA -- -- 0.05 g
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HD151012
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
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For further information write to:
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic Components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 585160
Copyright (c) Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
Colophon 2.0
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